Initially devised by Intel and subsequently supported by the PCI Special Interest Group (PCI-SIG), the Peripheral Component Interconnect bus has become established as arguably the most popular and ‘future proof bus standard available today. It avoids the IRQ conflicts of the ISA bus by using plug and play.

With plug and play, the system configures itself by allowing the PCI BIOS to access configuration registers on each add-in board at bootup time. As these configuration registers tell the system what resources they need (I/O space, memory space, interrupts, etc.), the system can allocate its resources accordingly, making sure that no two devices conflict.

The PCI BIOS cannot directly query ISA devices to determine which resources they need. This can sometimes give rise to problems in systems using both ISA and PCI. A PCI board’s 1/0 address and interrupt are not fixed, and can change every time the system boots.

PCI offers flexible bus mastering. This means that any PCI device can take control of the bus at any time, allowing it to shut out the CPU. Devices use bandwidth as available, even all the bandwidth, if no other demands are made for it.

Bus mastering works by sending request signals when a device wants control of the bus and the requestbeing
granted if data traffic allows it.

Because the PCI bus is not connected directly to the CPU (it is separated by an interface formed by a dedicated ‘PCI chipset’) the bus is sometimes referred to as a ‘mezzanine bus’. This technique offers two advantages over the earlier VL bus specification:

I. Reduced loading of the bus lines on the CPU (permitting a longer data path and allowing more bus cards to be connected to it).

II. Making the bus ‘processor independent’.

The original PCI bus was designed for operation at clock speeds of 33MHz. With a 32-bit data path, the 33MHz clock rate implies a maximum data transfer rate of around 130Mbyte/s (about the same as VL bus). Like the VL bus, the PCI bus connector is similar to that used for MCA. To cater for both 32- and 64-bit operation, PCI bus cards may have either 62 or 94 pins.

Later PCI implementations had a bus clock rate up to 66 MHz, giving up to 132 MB per second transfer rate over the 32-bit bus.

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