The effort required for the design of
an integrated circuit depends on the complexity of the circuit. The
requirement may range from several days effort for a single designer
to several months work for a team of designers.
Custom design of complex integrated
circuits is the most demanding. By contrast, semicustom design of LSI
and VLSI that utilize preexisting designs, such as standard cells and
gate arrays, requires less design effort.
IC design is performed at many
different levels and Fig. 8.9 is a non unique depiction of these
levels.
Level 1 presents the design in terms of
subsystems (standard cells, gate arrays, custom subcircuits, etc.)
and their interconnections. Design of the system layout begins with
the floor plan of level 3.
It does not involve the layout of
individual transistors and devices, but is concerned with the
geometric arrangement and interconnection of the subsystems.
Level 4 involves the circuit design of
the subsystems.
Levels 2 and 5 involve system and sub
circuit simulations, respectively, which may lead to modifications in
levels 1 and/or 4.
Discussion here will focus primarily on
the system design of level 1 and the subsystem circuit design of
level 4. Lumped under the fabrication process of level 7 are many
tasks, such as mask generation, process simulation, wafer
fabrication, testing, etc.
Broadly speaking, floor plan generation
is a part of layout. For large ICs, layout design is often relevant
to system and circuit design.
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