CMOS GATES BASIC AND TUTORIALS

WHAT ARE CMOS GATES? HOW CMOS GATES WORK?


CMOS gates are based on simple modifications to the CMOS inverter.

Figure 8.18(a) and Figure 8.18(b) show that the CMOS NOR and NAND gates are essentially CMOS inverters in which the load and driving transistor are replaced by series or parallel combinations (as appropriate) of PMOS andNMOStransistors, respectively.

Suppose the NOR gate of Fig. 8.18(a) is to have the same VDD and Vinv as the CMOS inverter of Fig. 8.17(a), then the equivalent Zpu and Zpd for the NOR gate should equal those for the inverter.

Since only one of the parallel pull-down transistors needs be on in the NOR to ensure VO = 0V, ZI = Zpd = 1/2 , as for the inverter. For the series load, however, ZL = 1/10 to give equivalent Zpu = 1/5 .

If the NAND gate of Fig. 8.18(b) is to have the same Vinv as the said inverter, similar arguments lead to ZI = 1/4 and ZL = 1/5 for the NAND.

Thus, KR = 0.4 for the inverter, 0.2 for the NOR, and 0.8 (closer to unity) for NAND. Hence, NAND is the standard gate in CMOS.

Another way of putting this is that for the given Z values, if the channel length L is constant, then the widths of the loads for the inverter, NOR, and NAND are in the ratio 1:2:1.

Thus, the NOR requires more chip area, and this larger area requirement increases with the number of inputs.